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Khare, Nilay
- A Study of Channel Estimation Techniques Based on Pilot Arrangement in OFDM Systems
Authors
1 Maulana Azad National Institute of Technology, Bhopal (M.P), IN
2 Electronics and Communication Department at Maulana Azad National Institute of Technology, Bhopal (M.P), IN
3 Computer Science and Engineering Department at Maulana Azad National Instt of Technology, Bhopal (M.P), IN
Source
Wireless Communication, Vol 3, No 2 (2011), Pagination: 114-120Abstract
The channel estimation techniques for OFDM systems based on pilot arrangement are investigated. The channel stimation based on comb type pilot arrangement is studied through different algorithms for both estimating channel at pilot frequencies and interpolating the channel. The estimation of channel at pilot frequencies is based on LS and LMS while the channel interpolation is linear interpolation, second order interpolation, low-pass interpolation, spline cubic interpolation, and time domain interpolation. Time-domain interpolation is obtained by passing to time domain through IDFT, zero padding and going back to frequency domain through DFT. In addition, the channel estimation based on block type pilot arrangement is performed by sending pilots at every sub-channel and using this estimation for a specific number of following symbols. We have also implemented decision feedback equalizer for all sub-channels followed by periodic block-type pilots. We have compared the performances of all schemes by measuring bit error rate with 16QAM, QPSK, DQPSK and BPSK as modulation schemes, and multipath Rayleigh fading and AR based fading channels as channel models. The simulation results show that combtype pilot based channel estimation with low-pass interpolation performs the best among all channel estimation algorithms.
Keywords
Channel Estimation, OFDM, Pilot Carrier, Rayleigh Fading.- Improved Parallel PageRank Algorithm for Spam Filtering
Authors
1 Department of Computer Science and Engineering, Maulana Azad National Institute of Technology, Bhopal - 462003, Madhya Pradesh, IN
2 Adobe Systems, Noida – 201304, IN
Source
Indian Journal of Science and Technology, Vol 9, No 38 (2016), Pagination:Abstract
Background/Objectives: PageRanking algorithm is a well known link based technique given by Google for indexing of its web pages. This algorithm works on the linking structure of web pages id est inbound and outbound links of pages. The existing Page Rank algorithm follows equal distribution law that is; it distributes the Page Rank of a web page evenly among all the outgoing links. The problem with the uniform distribution of Page Rank is that sometimes uninteresting pages got high Page Rank values. Methods/Statistical Analysis: This paper proposed an improved parallel Page Rank algorithm that un-uniformly distributes the Page Rank values among all the outgoing links. The proposed work has been implemented on NVIDIA Quadro 2000 GPU architecture using CUDA programming language. Findings: The proposed algorithm mitigates spam and provides better results in terms of computational time as compared to Parallel Page Rank, because it assigns higher priority to important pages and less priority to less important web pages. By assigning values in such a fashion important pages show an increase in the Page Rank value and unrelated pages that is spam pages show a decrease in Page Rank value. Application: The proposed work performs spam filtering by classifying important as well as irrelevant web pages.Keywords
CUDA, GPU, Non-Uniform Distribution, Parallel Page Rank, Spam Pages.- Modified Dijkstra’s Algorithm for Dense Graphs on GPU using CUDA
Authors
1 Department of Computer Science and Engineering, Maulana Ajad National Institute of Technology, Bhopal - 462003, Madhya Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 33 (2016), Pagination:Abstract
The objective of this research is to propose and implement a fast parallel Single source shortest path (SSSP) algorithm on Graphics Processing Unit (GPU) based highly parallel and cost effective platform for dense and complete graphs. The proposed algorithm is a variant of Dijkstra’s algorithm for SSSP calculation for complete and dense graphs. In place of relaxing all the edges of a selected node as in Dijkstra’s algorithm, it relaxes one-one selected edge of different nodes of the graph simultaneously at any iteration. This paper shows parallel implementation of both Dijkstra’s algorithm and our modified Dijkstra’s algorithm on a GPU-based machine. We evaluate these implementations on NVIDIA Tesla C2075 GPU- based machines. Parallel implementation of proposed modified Dijkstra’s algorithm gives a two to three times speed increase over a parallel Dijkstra’s algorithm on a GPU-based machine for complete and dense graphs. The proposed algorithm has minimized the number of edges relaxed by one parallel thread at any iteration of parallel Dijkstra’s algorithm.Keywords
CUDA, Graph Algorithm, GPU Computing, Parallel Dijkstra’s Algorithm, Parallel Single Source Shortest Path Algorithm.- Fuzzy and Parallel Enhanced Congestion Detection and Avoidance for Multiple Class of Traffic in Wireless Network
Authors
1 Department of Computer Science and Engineering, Maulana Azad National Institute of Technology, Bhopal – 462003, Madhya Pradesh, IN